The addition of a two level cache storage system, while substantially improving system performance for general data processing purposes, does not provide the same improvement in a vector processing operation. Further, the central processor, or main processor, is normally dominant in a data processing system which includes both. This requires that data fetched for use in the subservient vector processor must share storage access with the main processor, and this limits the vector processor's performance.
While cache systems have been effective to improve the mismatch caused by the disparate speeds of main storage and central processing units, the sensitivity of such units to error has required that the data passed through the cache be carefully checked for errors and, if possible, the error corrected. Conventional error checking and correction would burden the already tight timing characteristics of the cache organization, add cycles to the fetch access to accommodate the error checking and correction paths, or, even more complex, require a mechanism to interrupt the processor pipeline if an error is detected after the transfer of data.
An analysis of the technological characteristics of static random access memory used for cache storage revealed that soft failures such as those due to alpha particle contamination, are almost non-existent. This being the case, an effective error correction technique need consider only those hard bit failures, that is, those in which circuit failure has occurred. The ability to ignore conventional error checking and correction techniques means that additional machine cycles or substantial additional circuitry is not required. An additional complexity is also eliminated since the single byte handling of errors means that direct stores to cache, which may be from one byte to an entire line, can be handled the same way. Conventional error handling techniques do not lend themselves to single byte use, since they require a read-modify-write operation, thereby reducing the performance of the processor.
The invert-retry technique of this invention does not affect performance of the system unless an error occurs. Thus, normal operation of the system is completely unaffected and there is no time penalty. The invention nevertheless provides the capability of recovering from a hard bit error, allowing data to be recovered with minimal hardware needed to execute a short recover algorithm.
Storage transfers, that is, transfers of data from extended storage of real storage, have been handled by having the processor perform a fetch from one area of storage and then simply turn it around and store it in another location in storage. Such techniques suffer from several disabilities. First, there is the problem of the burden on the processor for performing a rather mundane task. Such excess processor time is either not available or, if available, is much better put to use elsewhere. In addition, the usual fetch instruction is not particularly well suited to the sort of transfer required for moving data between real and extended memory. While cache systems have been successfully used to improve the performance of storage systems by matching processor speeds to the fetching and storage of data, the housekeeping which accompanies such cache systems is not required in memory to memory transfers and slow down the transfer or utilize unnecessary hardware or, in some instances, both. Since extended storage is, by definition, not directly addressable by the processor, some method must be used to relocate data in the extended storage area before it can be used by the application programs being run on the system. The burden of transferring the data from extended storage to real storage degrades system performance, and, as a result, the full benefits of extended storage have not been realized.